Barrier Patents

last modified: 20 November 2002

In junction isolated integrated circuits, components are isolated by placing each in an n-type epi tub which is completely surrounded by the p substrate and a p-type isolation wall. Reverse biasing the resulting junction by tying the substrate to the most negative potential creates back-to-back reverse biased diodes between every component.

When attempts were made to power ICs with an AC source, it became difficult to keep the isolation region reverse biased by simply tying it to the DC ground potential. Later, when Power ICs began to drive inductive loads, one had similar problems when the inductive energy was pumped back into the chip beyond the supply rails.

Two general constraints are being fought: when an epi tub is pulled below substrate, it turns on a lateral NPN which pulls current from all other tubs, and when outputs exceed the positive rail, qoften there is a parasitic PNP turned on which dumps current to the substrate and locally may pull the substrate positive.

The following patents demonstrate the development of techniques in this area.
AC Line Operation of Monolithic Circuit
Patent no.:3,649,887
Inventor:Keller, Jean-Paul; Graf, Stefano A
Assignee:RCA Corporation
Date filed:August 11, 1969
Issued:March 14, 1972
Comments:Substrate is floated so epi can be pulled low w.r.t. ground
Junction-Isolated Monolithic Integrated Circuit Device with Means for Preventing Parasitic Transistor Action
Patent no.:3,931,634
Inventor:Knight, Mark Berwyn
Assignee:RCA Corporation
Date filed:June 14, 1973
Issued:January 6, 1976
Comments:An epi tub that becomes forward biased is surrounded by another epi region to act as a collector.
Integrated Full Wave Diode Bridge Rectifier
Patent no.:4,027,325
Inventor:Genesi, Robert C.
Assignee:Sprague Electric Company
Date filed:January 30, 1975
Issued:May 31, 1977
Comments:Refines the diode structures compared to above, makes very clear the action of the grounded parasitic collector.
Device for Protecting Against Leakage Currents in Integrated Circuits
Patent no.:4,466,011
Inventor:Van Zanten, Francois
Date filed:May 13, 1981
Issued:August 14, 1984
Comments:The added parasitic collector is tied to local substrate near control circuit to further reverse bias the substrate.
Integrated Device for Shielding Charge Injection into the Substrate, In Particular in Friving Circuits for Inductive and Capacitive Loads
Patent no.:4,890,149
Inventor:Bartotti, Franco; Ferrari, Paolo; Gatti, Maria T.
Assignee:SGS Microelettronica Spa
Date filed:September 21, 1987
Issued:December 26, 1989
Comments:A good NPN is put in parallel with the epi/iso diode, and the substrate region between power and circuitry is pulled below ground by that new transistor.
Integrated Device for Shielding Charge Injection into the Substrate
Patent no.:5,021,860
Inventor:Bertotti, Franco; Ferrari, Paolo; Gatti, Maria T.
Assignee:SGS-Thomson Microelectronics S.r.l.
Date filed:October 11, 1998
Issued:June 4, 1991
Comments:The added NPN above is placed between power and die edge, its collector pulls down the substrate between power and circuitry.
Power Integrated Circuit with Latch-Up Prevention
Patent no.:5,243,214
Inventor:Sin, Johnny K.O.; Singer, Barry M.; Mukherjee, Satyendranath
Assignee:North American Philips Corp.
Date filed:April 14, 1992
Issued:September 7, 1993
Comments:Uses parasitic NPN only, and location of epi, substrate regions are swapped from Bertotti
Structure to Protect Against Below Ground Current Injection
Patent no.:5,495,123
Inventor:Canclini, Athos
Assignee:SGS-Thomson Microelectronics Inc.
Date filed:October 31, 1994
Issued:February 27, 1996
Comments:A n+ and p+ barrier are inserted between power and low level circuits
Epitaxial Island with Adjacent Assymetrical Structure to Reduce Collection of Injected Current from the Island into Other Islands
Patent no.:5,514,901
Inventor:Peppiette, Richard M.; Cooper, Richard B.; Stoddard, Robert J.
Assignee:Allegro Microsystems Inc.
Date filed:May 17, 1994
Issued:May 7, 1996
Comments:Added NPN to pull substrate low is inverse NPN in same tub as power device
Separate Protective Transistor
Patent no.:5,545,917
Inventor:Peppiette, Richard M.; Cooper, Richard B.; Stoddard, Robert J.
Assignee:Allegro Microsystems Inc.
Date filed:May 17, 1994
Issued:August 13, 1996
Comments:A special (high Bvebo) NPN is added in separate tub as in Bertotti.
Protection Against Adverse Parasitic Effects in Junction-Isolated Integrated Circuits
Patent no.:5,834,826
Inventor:Menegoli, Paolo
Assignee:STMicroelectronics S.r.l.
Date filed:May 9, 1997
Issued:November 10, 1998
Comments:Parasitic collector is sensed and protection circuitry activated
Method for Suppressing Parasitic Effects in a Junction-Isolation Integrated Circuit
Patent no.:6,248,616
Inventor:Ravanelli. Enrico Maria; Pozzoni, Massimo; Pedrazzini, Giorgio; Ricotti, Giulio
Assignee:STMicroelectronics S.r.l.
Date filed:January 26, 2000
Issued:June 19, 2001
Comments:The voltage of the Iso is sensed versus the wafer backside; depending on direction of parasitic current, the substrate is switched between parasitic collector and circuit ground.